A Closed Loop Delay Compensation Technique to Mitigate the Common Mode Conducted Emissions of Bipolar PWM Switched Circuits

This paper presents the design of a new closed loop technique that reduces the common mode conducted emission. This technique can be applied to all switching circuits in which couples of outputs are modulated by a bipolar PWM signal. It is based on the compensation of the delay between complementary output switching edges, using a simple sensing circuit and a low computational effort software algorithm, which is implemented in a microcontroller driving the switching circuit. One of the main advantages of the proposed technique is the reduction of the disturbance energy, without affecting the system efficiency. The technique is practical to implement, and the measurements performed on a power inverter prototype confirm the theoretical analysis outcomes about the reduction of the conducted emission in the lower-to-medium frequency range

Investigation on the Susceptibility to EMI of Second-Order ΔΣ Modulators

This paper analyzes the effects of radio frequency interference on second order ΔΣ modulators based on continuoustime (CT) and on discrete-time (DT) architectures. Specifically, Modulators used for the acquisition of sensor signals are targeted, which can operate with moderate clock rates due to the relatively small bandwidth of the signal to be acquired. A continuous wave interference with frequency above that of the modulator clock signal is superimposed onto the nominal input one with the purpose of evaluating the degradation of their performance, and more specifically their capability to demodulate out of band interference

An Adaptive Method to Reduce Undershoots and Overshoots in Power Switching Transistors Through a Low Complexity Active Gate Driver

Active gate drivers lend themselves well to reducing over- and under- voltages during the commutations of hard switched power transistors, as well as to damping resonances. However, their control strategy is a major challenge, as it should account for variations of operating condition, parameter spread, and non linearities of the driven transistor. This paper proposes an effective control method to reduce overshoots and undershoots in a power transistor driven by an active gate driver. The modulation pattern is modified on-the-fly and none a-priori characterization is required. The presented method modifies the timing parameter to attain almost zero over- and under- voltages with the lowest power losses. This is achieved by combining a low complexity active gate driver with the measurements of peak values of the drain-source voltage. The technique was experimentally assessed for a 48-12 V DC-DC converter, and resulted in better switching performance than standard solutions and open loop control

Investigations on the Use of the Power Transistor Source Inductance to Mitigate the Electromagnetic Emission of Switching Power Circuits

With power designers always demanding for faster power switches, electromagnetic interference has become an issue of primary concern. As known, the commutation of power transistors is the main cause of the electromagnetic noise, which can be worsened by the presence of unwanted oscillations superimposed onto the switching waveforms. This work proposes a solution to mitigate the oscillations caused by the turn-on of a power transistor by exploiting its source inductance plus an external one. In this context, an optimization method is proposed to find the optimal value of the source inductance as a trade-off between oscillation damping and power dissipation. The experimental results performed on a prototyped power converter assess the proposed technique as the spectrum of the conducted emission is attenuated by 20 dB at the oscillation frequency. With respect to traditional solution based on snubbers, the proposed solution results in a similar oscillation damping, but with a 0.5% higher power efficiency

Evaluation of the Common Mode and the Differential Mode Components from Conducted Emission Measurements

The design of the power supply electromagnetic interference filter needed to mitigate the conducted emission of electronic modules can be performed best if the magnitude of the common mode (CM) and that of the differential mode (DM) interference are known. In common test setups, the two terms can be obtained from the signals measured at the line impedance stabilization networks (LISNs) output ports using DM and CM rejection networks or through the postprocessing of the output signals in the time domain. Both these approaches rely on the perfect matching of the LISNs internal filters, which is not realistic. The LISNs mismatch allow the DM to be measured as CM and vice versa. In this work, the influence of the LISNs mismatch on the separation of CM and DM is investigated and a fast and accurate method to do that is proposed